Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode.
Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores.
| EN | Timer enable bit. When 0, the timer will not increment automatically. |
| FULLSPEED | If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input. |
| DBGPAUSE_CORE0 | If 1, the timer pauses when core 0 is in the debug halt state. |
| DBGPAUSE_CORE1 | If 1, the timer pauses when core 1 is in the debug halt state. |